1. Field of the Invention
The present invention relates to a high-voltage, high-cutoff-frequency electronic metal-oxide semiconductor (MOS) device. Hereinafter, reference will be made, without limitation, to a DMOS device.
2. Description of the Related Art
As is known, double-diffused metal-oxide semiconductor (DMOS) high-voltage devices (with a voltage higher than 20 V) have a limited cutoff frequency. However, there are some applications where a high cutoff frequency is requested, as for example in telecommunications and especially in wireless appliances. To try to overcome this inconvenience, suitable technological solutions are studied to reduce the parasitic capacities associated with the devices. In fact, in DMOS devices, the cutoff frequency Ft is given, in a first approximation, by:                               F          t                =                              g            m                                2            ⁢            π            ⁢                                                   ⁢                          C              gd                                                          (        1        )            where gm is the transconductance of the device and Cgd is the parasitic capacity existing between the gate electrode and the drain region.
From (1) it is clear that, to maximize the cutoff frequency Ft, it is necessary to maximize the transconductance gm and/or to minimize the parasitic capacity Cgd.
The optimization of the parameter in the numerator is easy in case of power structures, which have a large channel perimeter; in fact in this case it is possible to maximize the perimeter of the integrated device with the minimum length of the channel, for example making structures wherein the source is completely surrounded by the drain region, so as to obtain the maximum transconductance gm associated with the respective parasitic capacity Cgd.
In contrast, in the case of minimum structures (that is structures designed with the minimum dimensions compatible with the existing voltage requirements), the layout is never optimized as regards the cutoff frequency. In fact, these structures present field edge structures forming field plates and are generally formed by the gate polysilicon so as to reduce the electric field associated with the geometric discontinuity constituted by the field oxide (tip effect).
These edge structures surround the whole source region so as to ensure that the device withstands the high voltages. An example of DMOS with a field plate of the type described is shown in FIG. 1, where a pocket 1 of N-type, forming a drain region, is surrounded by an insulating structure 2, made in any way. A field oxide layer 3 extends on top of the pocket 1 and has a first opening 8, which surrounds an active area 4 and a second opening 5 where a drain contact region 6 is formed, of N+-type. A body region 10, of P-type, is formed in the active area 4 and houses a source region 11, of N+-type, and a body contact region 12, of P+-type. A gate region 15 extends along the whole edge of the first opening 8, partly on the bird's beak-shaped portion of the field oxide layer 3, partly on top of the active area 4. The gate region 15 is electrically insulated, with respect to the pocket 1, by a thin gate oxide layer, not shown, and therefore forms, with the pocket 1, a parasitic capacity Cgd, represented by dashed lines. The source region 11 and the body region 10 (through the body contact region 12) are electrically connected through a source/body contact line SB; the gate region 15 is biased through a gate contact G and the N-pocket is biased through a drain contact D formed on the drain contact region 6.
FIG. 2 shows the profile of the masks used for forming the device of FIG. 1; in particular, 20 indicates the drain mask; 21 the active area mask; 22 the gate mask; 23 the source mask and 24 the body contact mask. The gate region 15 is dashed, to show its overall form, as a closed loop. The mask used for forming the body region 10 is not visible, since it coincides with the three outer sides of masks 23 and 24. FIG. 2 further shows the drain contact D as well as the source contacts S and body contacts B connected to the source/body contact line SB.
In the device in FIG. 1, in presence of a large parasitic capacity Cgd (due to the large facing area between the gate region 15 and the drain region—pocket 1—), there is a low transconductance (since the only channel active part is the portion of the body region 10 arranged between the source region 11 and the pocket 1, below the gate region 15; the portion of the body region 10 arranged between the body contact region 12 and the pocket 1 does not contribute to the formation of the device channel.
This conformation therefore does not allow a high cutoff frequency; consequently, while a power device has for example, in a 200 V technology with a silicon-on-insulator (SOI) substrate, a cutoff frequency Ft=3.2 GHz, a minimum type device of the same voltage class has a cutoff frequency Ft=2.26 GHz (exactly proportional to the ratio gm/Cgd).